Field of Invention
This invention relates to a structure of a semiconductor device, particularly a structure of an electrostatic discharge (ESD) device.
Description of Related Art
With continuous reduction in dimensions, the integrated circuits are more easily damaged by ESD, so ESD protection devices are usually designed in integrated circuits. One type of ESD protection device is the multi-finger transistor, which usually includes multiple NMOS elements arranged in parallel. The electrostatic discharge of such a device is based on the switching of the parasitic bipolar junction transistors (BJT) each formed by the source and drain regions of a NMOS element and the substrate.
However, since the central NMOS elements are more distant from the pick-up regions of the substrate, the base resistance of the corresponding parasitic BJT is higher. Meanwhile, since the breakdown voltages of the drain regions of all NMOS elements are the same, the magnitude of the breakdown current from each drain to the substrate is uniform. Hence, in an ESD event, the junction voltage (V=I×R) between the collector (drain) and the base (substrate) of the central BJTs is higher, so the central BJTs are switched on first. The details can be found in “An analytical model of positive H.B.M ESD current distribution and the modified multi-finger protection structure,” Proc. Int. Symp. on Physical and Failure Analysis of Integrated Circuits, 1999, pp. 162-167.
As a result, most ESD current will flow through the central NMOS, and contact spiking or junction punch easily occurs to the drain region thereof to significantly deteriorate the ESD protection function of the multi-finger transistor.